This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-039968, filed Feb. 17, 2000.
The present invention relates to a semiconductor device using a fuse/anti-fuse system and a method of manufacturing the same.
In recent years, the semiconductor device is being made finer and finer to a high degree. In this connection, the element isolating region for isolating the element is formed mainly by a STI (Shallow Trench Isolation) method in place of the conventional LOCOS (Local Oxidation Of Silicon) method. It should be noted, however, that the film formed by the STI method has a very high surface flatness, with the result that, in the subsequent step of forming the gate electrode, it was necessary to employ the stepping process for forming an aligning mark.
FIGS. 28 to 33 are cross sectional views collectively showing the conventional process of manufacturing a semiconductor device. The conventional process of forming a semiconductor process will now be described with reference to FIGS. 28 to 33.
In the first step, a first concave portion 42 providing an element isolation region and a second concave portion 43, which is used in the subsequent lithography process for forming an aligning mark, are formed in a silicon substrate 41 by a lithography technology and an RIE (Reactive Ion Etching) method, as shown in FIG. 28.
In the next step, for example, a silicon oxide film 45 is formed on the entire surface so as to fill the first and second concave portions 42 and 43 with the silicon oxide film 45, as shown in FIG. 29. Then, the silicon oxide film 45 is removed by a CMP (Chemical Mechanical Polish) method until the surface of the silicon substrate 41 is exposed to the outside, thereby forming an element isolating region 46 of an STI structure in the first concave portion 42.
After formation of the element isolating region 46, a resist film 47 is formed on the entire surface, followed by patterning the resist film 47 by the lithography technology and the RIE method, as shown in FIG. 30. Then, the silicon oxide film 45 within the second concave portion 43 is removed by the wet etching performed with the patterned resist film 47 used as a mask, thereby an aligning mark portion 53 is formed in the second concave portion 43. Followed by removing the resist film 47. In the following description, the step of removing the silicon oxide film 45 buried in the second concave portion 43 is called the stepping process.
In the next step, a gate insulating film 48 is formed on the entire surface, as shown in FIG. 31, followed by forming a polycrystalline silicon (polysilicon) film 49 on the gate insulating film 48. Further a tungsten film 50 is formed on the polysilicon film 49, and a silicon nitride film 51 is formed on the tungsten film 50.
Then, the silicon nitride film 51, the tungsten film 50, the polysilicon film 49 and the gate insulating film 48 are selectively removed by the lithography technology and the RIE method, as shown in FIG. 32. As a result, a gate electrode 52 is formed on a predetermined element region 46a. Incidentally, the gate insulating film of the gate electrode 52 is denoted by a reference numeral 48a. 
In the next step, a gate side wall 55 is formed on the side surface of the gate electrode 52, and source-drain regions 56 are formed in surface regions of the silicon substrate 41 in contact with the edge portions of the gate insulating film 48a by the known technology, as shown in FIG. 33. Then, an interlayer insulating film 57 is formed on the entire surface, followed by forming a contact plug 58 and an upper wiring layer 59 and subsequently forming another interlayer insulating film 60 on the entire surface.
Where the tungsten film 50, etc. is used as a part of the gate electrode 52 as described above, it is difficult to read the difference in the film quality of the underlying layer by an optical method because the tungsten film 50 has a high reflectance. Therefore, if the stepping process for forming the aligning mark portion 53, which is shown in FIG. 30, is omitted, it is impossible to read the aligning mark portion 53 by an optical method in the case of employing because the aligning mark portion 53 is no step, for example, the STI method that permits the formed film to have a high degree of surface flatness. It follows that the problem of the deviation in the alignment between the element isolating region 46 (or element region 46a) and the gate electrode 52 is rendered serious.
As described above, the lithography step and the etching step included in the stepping process are indispensable for avoiding the problem of the deviation in the alignment. However, since these steps are used solely for the stepping of the aligning mark portion 53, it was desirable to omit these steps or to effectively utilize these steps.
On the other hand, in, for example, a DRAM (Dynamic Random Access Memory), the apparatus is equipped in many cases with a remedy circuit for substituting an auxiliary cell for the defective cell in order to improve the yield of the product. For the judgment of the cell that is to be renewed, it was customary to use a fuse of the type that the wiring made of mainly aluminum is fused away by a laser beam. On the other hand, proposed is an anti-fuse in which the judgment is performed by breaking the gate insulating film in a predetermined portion.
The anti-fuse is expected to produce various merits. For example, the anti-fuse is expected to decrease the area occupied within the chip and to permit replacing the final defective cell after sealing the package. Also, in the anti-fuse, a desired gate insulating film is broken to make the device conductive by applying a voltage higher than the breakdown voltage. Therefore, in general, the anti-fuse is connected to a high voltage generating circuit for breaking the gate insulating film and to a judging circuit for detecting whether the anti-fuse portion is broken or not. It follows that, in breaking the anti-fuse portion, the gate insulating film in the judging circuit portion also is damaged to some extent. Such being the situation, it was desirable to permit the anti-fuse portion to be broken with a reasonably low voltage while suppressing the damage done to the judging circuit and other portions as much as possible.
Also, in order to suppress the increase in the number of manufacturing steps, it is desirable to form the gate insulating film in the anti-fuse portion simultaneously with formation of the gate insulating film of the MOS transistor. However, it was difficult to form the gate insulating film of the anti-fuse portion having a low breakdown voltage simultaneously with formation of the gate insulating film included in the ordinary transistor and having a high reliability. Under the circumstances, it was difficult to put to the practical use the anti-fuse utilizing the gate insulating film formed for the transistor.
An object of the present invention, which has been achieved in an attempt to solve the above-noted problems, is to provide a semiconductor device that permits forming a gate insulating film having a desired breakdown voltage without increasing the number of manufacturing steps by applying the stepping process for forming an aligning mark to the formation of the anti-fuse and a method of manufacturing the particular semiconductor device.
According to a first aspect of the present invention, which permits achieving the object described above, there is provided a semiconductor device, comprising a concave portion formed in a semiconductor substrate, a first gate insulating film formed selectively on the semiconductor substrate, a second gate insulating film formed in at least the bottom surface of the concave portion, a first conductive film formed on the first gate insulating film, and a second conductive film formed on the second gate insulating film.
It is possible for the second gate insulating film and the second conductive film to be formed on the bottom surface of the concave portion, on at least one side surface of the concave portion and on the semiconductor substrate. It is also possible for the surface of the first conductive film to be flush with the surface of the second conductive film formed on the semiconductor substrate.
It is possible for the second gate insulating film to be formed in the corner portion of the concave portion.
It is also possible for an insulating film to be formed on the second conductive film and for the concave portion to be filled with the insulating film, the second gate insulating film and the second conductive film. Further, it is possible for the concave portion to be filled with the second gate insulating film and the second conductive film and for the surface of the second conductive film to be substantially flat.
It is possible for the semiconductor substrate to be an SOI substrate.
It is possible for the semiconductor device to further comprise an element isolating region formed within the semiconductor substrate such that the second gate insulating film and the second conductive film are allowed to extend over the element isolating region, a contact electrically connected to that portion of the second conductive film which is positioned on the element isolating region, and a wiring electrically connected to the contact.
It is possible for a plurality of concave portions to be formed in the semiconductor substrate such that these concave portions are filled with the second gate insulating film and the second conductive film and for the surface of the second conductive film to be substantially flat.
It is possible for a plurality of gate electrodes each consisting of the second conductive film to be formed in the concave portions.
It is possible for the impurity concentration in the second conductive film to be higher than that in the semiconductor substrate.
The second insulating film functions as the insulating film for the anti-fuse portion or for the capacitor element.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming first, second and third concave portions in a semiconductor substrate; burying an insulating film in the first, second and third concave portions, followed by planarizing the surface of the insulating film until the surface of the semiconductor substrate is exposed to the outside so as to form an element isolating region within the first concave portion; removing the insulating film from the second and third concave portions so as to form a aligning mark portion in the second concave portion; forming a gate insulating film on the entire surface; forming a conductive film on the gate insulating film; and selectively removing the conductive film so as to form a first gate electrode on the semiconductor substrate, and to form a second gate electrode in the third concave portion.
It is possible to form a gate insulating film on the entire surface, with the insulating film formed within the third concave portion partly left unremoved.
It is possible to form the second gate electrode on the bottom surface of the third concave portion, on both side surfaces or one side surface of the third concave portion, and on the semiconductor substrate.
It is possible to form the second gate electrode in a manner to fill the third concave portion.
It is possible to form the second gate electrode in a manner to extend from within the third concave portion onto the element isolating region and to form the contact on that portion of the second gate electrode which is positioned on the element isolating region.
It is possible to form a plurality of third concave portions. It is also possible to form a plurality of second gate electrodes within the third concave portions.
It is possible for the impurity concentration of the conductive film to be higher than that of the semiconductor substrate.
The second gate electrode functions as the gate electrode for the anti-fuse portion or for the capacitor element.
As described above, the present invention provides a semiconductor device that permits forming a gate insulating film having a desired breakdown voltage without increasing the number of manufacturing steps by applying the stepping process for the aligning mark to the anti-fuse formation and a method of manufacturing the particular semiconductor device.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.